Conventional Field-Effect Transistors (FETs) comprise one transport channel, which is generally induced as an inversion layer by the application of a gate voltage above a threshold value. It has one source and one drain. Although a FET may have one or more gates, typically there is only one top gate which is formed above the transport channel having an appropriate thin gate insulator layer. Additionally, Field-Effect Transistors (FETs) having a back gate have also been reported. Moreover, there are also FIN-FETs where the gate region surrounds the semiconductor body between the source and drain regions. All of these structures have the common characteristic that there is one inversion channel which is connected to one drain and one source. Conventional FETs are well known to realize static random access memory SRAM cells using two cross-coupled inverters (each inverter having two transistors either in n-MOS or CMOS configurations) with two access transistors. In addition, dynamic random access memory (DRAM) cells are realized using conventional FETs using one-transistor (1-T) and one storage capacitor. This 1-T DRAM cell is widely used. However, these conventional FET based memories only process 1-bit at one stage.